The present invention relates generally to integrated circuit (IC) designs, and, more particularly, to a test structure array that can accommodate various types of test structures.
In state-of-the-art Complementary Metal-Oxide-Semiconductor (CMOS) logic processes, variations of device electrical parameters resulting from the lithographic proximity, etching loading effect among the various pattern density area, chemical-mechanical polishing non-planarization, etc., are dominating and worsening the variability of circuit performance as well as degrading the product yield. In order to sustain circuit performances and product yields, foundries provide process characteristic related design rule sets, which are often called Recommended Rules (Rrules). The more complex the processes are, the more device and process parameters are needed to be characterized.
Traditionally, production monitoring test chips are placed in small scribe lines between product dies. But its limited space cannot accommodate large numbers of test devices. The space required for large number of test devices is only found on large test chips, usually processed on a single fab lot for characterization purposes. While using the test chips is useful, they provide no assistance for on-going production monitoring nor to help debug actual circuits that are not built onto the test chips.
Although the number of test devices is increasing, field size of photolithography is still unchanged at a limiting 33×26 mm2. To compromise the limited photolithography field size and the need to characterize a large number of test devices, various test vehicle design methodologies adopting addressable array and multiplexed cell accesses have been proposed.
Individual test devices normally occupy a very small area. If placing them in an addressable array, i.e., a test device that forms a part of a unit cell of the array, then a large quantity of test devices can be accommodated in a two dimensional space, yet can still be addressed by a small number of addresses. Multiplexed cell accesses are for switching access to a larger number of test devices through a small number of input/output nodes, which are known as the ‘probe pads’ on a probe card.
However, as each test device has different connections, if a corresponding control circuit is also different from one unit cell to another, then designing a large array of unit cells containing various test devices will be a substantial endeavor and often not practical. Besides, additional parasitic resistance introduced by the multiplexing scheme can also prohibit many kinds of measurements due to excessive background leakage.
As such, there is a need for a multiplexed addressable test structure array with a common unit cell construction, which can minimize effects caused by parasitic resistance and non-linear characteristic of a multiplexing scheme.